1. Field of the Invention
The invention relates to the field of semiconductor device testing and packaging and more particularly to integrated circuit bond pad testing and packaging.
2. Description of Related Art
In the manufacture of semiconductor devices, it is advisable that such devices be tested at the wafer level to evaluate their functionality. The process in which devices in a wafer are tested is commonly referred to as "wafer sort." Testing and determining design flaws at the wafer level offers several advantages. First, it allows designers to evaluate the functionality of new devices during development. Increasing packaging costs also make wafer sorting a viable cost saver, in that reliability and functionality of each die on a wafer may be tested before incurring the higher costs of packaging. Measuring reliability also allows the performance of the production process to be evaluated and production consistency rated, such as for example by "bin switching" whereby the performance of a die is downgraded because that die's performance did not meet the expected criteria.
FIG. 1 illustrates a surface view of the top side of an integrated circuit device. Metal interconnect lines and components of integrated circuit device 11 are formed on an underlying silicon substrate. The side of the silicon substrate on which the integrated circuit is formed shall herein be referred to as the top side of the silicon substrate. As illustrated in FIG. 1, bond pads 13 are located along the periphery of integrated circuit device 11. In the center of integrated circuit device 11 is the active region 12 containing the majority of the high density, active circuitry of integrated circuit device 11. To activate the circuitry within active region 12, it is necessary to supply voltage signals to bond pads 13. These voltage signals are supplied to bond pads 13 through a package to which integrated circuit device 11 is affixed.
FIG. 2 illustrates a cross-section of integrated circuit device 11 after packaging. After integrated circuit device 11 is affixed to package substrate 15, individual bond wires 14 are used to electrically couple each bond pad 13 to a corresponding pad on package substrate 15. Each corresponding pad 13 on package substrate 15 is then individually coupled to an external pin 16. The packaged integrated circuit device of FIG. 2 may then be placed within a socket in order to electrically couple external pin 16 to drivers that supply the necessary voltage signal to activate integrated circuit device 11. As illustrated in FIG. 2, integrated circuit device 11 is mounted to package substrate 15 with its top-side facing away from package substrate 15. In this manner, once integrated circuit device 11 is activated through package pin 16, the internal, active region 12 may be accessed and probed for testing since neither bond pads 13, package substrate 15, nor bond wires 14 obscure access to this region of integrated circuit device 11.
FIG. 3 illustrates a top-side view of a second bond pad configuration on an integrated circuit device. As illustrated in FIG. 3, bond pads 21 of integrated circuit device 20 are formed along the top of the entire integrated circuit device so that the bond pads now reside directly over the active circuitry region of integrated circuit device 20. By forming bond pads in both the center and periphery of integrated circuit device 20, more bond pads can be placed across the surface of the device than can be placed only within the peripheral region. In addition, active circuitry which underlies bond pads 21 of integrated circuit device can be directly coupled to its nearest bond pad using relatively short interconnect lines. This minimizes the resistive, capacitive, and inductive effects associated with routing interconnect lines over long distances, improving speed performance.
FIG. 4 is an illustration of a cross-section of integrated circuit device 20 after mounting to a package substrate 22. In order to mount integrated circuit device 20 to package substrate 22, solder balls 24 are placed on each of bond pads 21 to electrically couple each bond pad 21 to its corresponding solder ball on package substrate 22. Each corresponding solder ball on package substrate 22 is, in turn, coupled to an external pin 23. Integrated circuit device 20 is mounted to package substrate 22 with its top-side facing towards the package substrate. In other words, in comparison to the method used to mount integrated circuit device 11 to its package substrate in FIG. 2, integrated circuit device 20 is "flipped." For this reason, the design of integrated circuit device 20 illustrated in FIG. 3 and its subsequent packaging method illustrated in FIG. 4 is referred to as flip-chip technology. The technology is also known as Controlled Collapsable Chip Connection (C4), named after the package mounting technique of using solder to replace bond wires.
Integrated circuit device 11 (as shown in FIG. 1) or integrated circuit device 20 (as shown in FIG. 3) illustrate bond pads 13 and 21, respectively, available for electrical coupling to a corresponding pad on package substrate, 15 and 22, respectively. In general, after the device is made, bond pads 13 and 21, respectively, lie beneath dielectric layers and must be exposed for bonding to package 15 and 22, respectively. In the typical process, bond pads 13 and 21, respectively, are covered by a hard passivation layer of, for example, silicon nitride (Si.sub.3 N.sub.4). This hard passivation layer is covered by a soft passivation layer of, for example, a photodefinable polyimide. The hard and soft passivation layers protect the device from the ambient, for example, scratches, moisture, and impurities. The bond pads of the integrated circuit device are exposed by removing the hard and soft passivation layers over the top surface of the bond pads. Techniques for opening a bond pad are well known in the art.
In the case of the C4 platform devices (as illustrated in FIGS. 3-4), once the bond pads are opened, a base layer of conductive material is placed over the bond pad. In one example, the base layer of conductive material includes a first layer of titanium uniformly deposited over the wafer to a thickness of approximately 500 angstroms (.ANG.) to improve the contact resistance between the bond pad and the solder bump. Next, a second base layer of conductive material of, for example, Nickel-Vanadium to a thickness of approximately 3600 .ANG. is uniformly deposited as a barrier layer. A photoresist is then spun over the surface of the wafer and patterned to expose only the bond pad surfaces. Next, Lead-Tin (Pb--Sn) solder is deposited over the exposed bond pads through an electroplating process. The resist is then removed and the solder bumps are tested by a wafer sort process to determine the electrical fitness of the device.
FIG. 5 shows a prior art solder bump undergoing an E-Test. Wafer testing and sorting typically involves the use of probing technology wherein a probe card 30 containing a probe feature 35 engages solder bump 40 on a chip of the wafer so as to electrically test the underlying integrated circuit device 25. Probe feature 35 contacts the top surface of bump 40 that is formed over bond pad 27 of integrated circuit device 25.
When testing a solder bump of a device on a wafer such as illustrated in FIG. 5, it is often hard to prevent the oxidation of bump surface 45 prior to testing. Therefore, most categories of probing or testing utilize some form of "scrub" at the touch-down phase of a probe feature to a solder bump. Scrub applies to the process where the probe features on a probe card pierce (scrub) the layer of oxide that grows quickly on an exposed solder bump. Generally, scrub applies to the destruction of any non-conductive layer that produces a barrier between the test probes of a probe card and the solder bump. The purpose of the scrub is to break through the non-conductive layer on the solder bump in order to establish a good electrical contact between the probe features and the solder bump. Scrub occurs when the components of the probe card and its handler forces the wafer, and subsequently the solder bumps of a device of a wafer, against the probe features on the probe card causing the probe features to deflect and the non-conductive layer to break. Scrub is generated by a small horizontal movement of each probe feature across the surface of each corresponding solder bump as the probe features deflect. As the probe features move across the solder bump, they break and penetrate the non-conductive oxide layer, for example a lead oxide (PbO) layer, thereby establishing a good electrical contact between the probe features and the solder bumps.
As illustrated in FIG. 5, top surface 45 of solder bump 40 is very rough. The roughness of top surface 45 is the result of the electroplating process used to deposit the solder bump. When probe card 30 attempts to probe solder bump 40 with probe feature 35, asperities break off and stick to the tip of probe feature 35 causing probe feature 35 to become dirty and require cleaning. The tip of probe feature 35 collects asperities dislodged from top surface 45 of solder bump 40 during scrubbing, and probe feature 35 requires frequent cleaning. Frequent cleaning results in a shorter life of probe card 30 which translates to a considerable expense for wafer testing.
The presence of asperities or a rough surface 45 of solder bump 40 also results in a non-uniform contact area for probe feature 35. Thus, it is difficult to ascertain whether probe feature 35 makes good electrical contact with the top surface 45 of solder bump 40. This effects the reliability and repeatability of the testing. The presence of asperities on as-electroplated bumps also increases the contact resistance between solder bump 40 and probe feature 35. The soiling of the probe card, unreliable results, and increased contact resistance results in, perhaps inaccurate, lower test yields and, for example, bin switching, i.e., the recharacterization of device performance based upon testing results.